1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a driving device and driving method of a plasma display panel, which can lower power consumption and enable high-speed driving.
2. Description of the Background Art
A plasma display panel (hereinafter, referred to as “PDP”) is a display device using a phenomenon that a phosphor emits visible light when it is excited by ultraviolet ray generated by gas discharge. A PDP has some advantages including that it is thinner and lighter than a cathode ray tube (CRT) that has ever been the mainstream of a display device, and a high-definition large screen PDP can be produced. A PDP is comprised of a matrix of many discharge cells, and each of the discharge cells forms a pixel of a display.
FIG. 1 is an oblique perspective diagram illustrating a discharge cell of an existing alternate current (hereinafter, referred to as “AC”) sheet discharge type PDP. Referring to FIG. 1, a discharge cell of a three-electrode AC sheet discharge type PDP includes a scan electrode 12Y and a sustain electrode 12Z that are formed on an upper substrate 10, and an address electrode 20X that is formed on a lower substrate 18. An upper dialectic layer 14 and a protective film 16 are laminated on the upper substrate 10 that the scan electrode 12Y and the sustain electrode 12Z are formed in parallel. Wall charges generated in the plasma discharge are accumulated on the upper dialectic layer 14. The protective film 16 protects damage on the upper dialectic 14 by sputtering generated in the plasma discharge, and increases emission efficiency of secondary electrons. Magnesium oxide (MgO) is generally used for the protective film 16.
A lower dialectic layer 22 and a division wall 24 are formed on the lower substrate 18 that the address electrode 20X is formed, and a phosphor 26 is applied on the surface of the lower dialectic layer 22 and the division wall 24. The address electrode 20X is formed in the direction that crosses the scan electrode 12Y and the sustain electrode 12Z. The division wall 24 is formed in parallel with the address electrode 20X and prevents ultraviolet rays and visible light that are generated in the discharge from leaking into the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated in the plasma discharge, and emits either of red, green, or blue visible light. To generate the gas discharge, inert gases is injected into the discharge space, which is formed among the upper substrate 10, the lower substrate 18, and the division wall 24.
To realize the gradation sequence of an image, one frame of the PDP is divided into some sub-fields with different emission frequency, and the time division driving is conducted. Each sub-field is divided into a reset period RPD to reset a prior screen, an address period APD to select a scan line and select a cell with the selected scan line, and a sustain period SPD to realize the gradation sequence according to the discharge frequency.
The reset period RPD is divided into a full write period that a ramp pulse are provided, and a stabilization period that a stabilization pulse is provided. For example, as is shown in FIG. 2, when an image is displayed with 256-gradation sequence, one frame period, which corresponds to one-sixtieth second (16.67 ms), is divided into eight sub-fields SF1 through SF8. The address period APD in each of the sub-fields has the same length, but length of the sustain period SPD is getting longer in each of the sub-fields at the rate of 2n(n=0, 1, 2, 3, 4, 5, 6, 7).
Referring to FIG. 3, an existing driving device of an AC sheet discharge type PDP includes a PDP 30 that a [m×n] matrix of discharge cells 1 is distributed so that it is connected to scan electrode lines Y1 through Ym, sustain electrode lines Z1 through Zm, and address electrode lines X1 through Xn, a scan driving part 32 to drive the scan electrode lines Y1 though Ym, a sustain driving part 34 to drive the sustain electrode lines Z1 through Zm, and a first address driving part 36A that drives odd-numbered lines of the address electrode lines (X1, X3, . . . Xn-3, Xn-1) and a second address driving part 36B that drives even-numbered lines of the address electrode lines (X2, X4, X6 . . . Xn-2, Xn).
The scan driving part 32 provides a scan pulse and a sustain pulse with the scan electrode lines Y1 through Ym in order, so that each of the discharge cells 1 is sequentially scanned on a line-by-line basis, and it sustains the discharge in the [mxn] discharge cells 1. The sustain driving part 34 provides sustain pulses with all of the sustain electrode lines Z1 through Zm. The first address driving part 36A and the second address driving part 36B provide image data with the address electrode lines X1 through Xn, so that it can synchronize with scan pulses. The first address driving part 36A provides image data with odd-numbered lines of the address electrode lines (X1, X3, . . . Xn-3, and Xn-1), and the second address driving part 36B provides image data with even-numbered lines of the address electrode lines (X2, X4. . . Xn-2, and Xn).
In the AC sheet discharge type PDP that is driven as described above, more than hundreds of volts of high-voltage is required for the address discharge and the sustain discharge. Accordingly, the electric power recovery devices are installed in the scan driving part 32, the sustain driving part 34, and address driving parts 36A and 36B to minimize driving power required for the address discharge and the sustain discharge. The electric power recovery devices recover voltage that is charged in a panel, and re-power the voltage as the driving voltage in the next discharge.
FIG. 4 is a diagram illustrating an existing electric power recovery device that is installed on the anterior end of an address driving part. Referring to FIG. 4, an existing electric power recovery device 40 includes an inductor L that is connected between a first address driving part 36A and an energy recovery capacitor Cs, a first switch S1 and a third switch S3 that are connected between the energy recovery capacitor Cs and the inductor L in parallel, and a second switch S2 and a fourth switch S4 that are connected between the inductor L and the first address driving part 36A in parallel. The panel capacitor Cp expresses the electric capacitance in the discharge cells of PDP equivalently.
The second switch S2 is connected to a voltage Vd, and the fourth switch S4 is connected to a base voltage GND. The energy recovery capacitor Cs recovers and charges voltage that is charged in the panel capacitor Cp in the address discharge, and re-power the charged voltage with the panel capacitor Cp. The energy recovery capacitor Cs charges the voltage of Vd/2, which corresponds to half of the address voltage Vd. The inductor L and the panel capacitor Cp form a sympathetic vibration circuit. When the first through fourth switches S1 though S4 are turned on or turned off, voltage is charged in the energy recovery capacitor Cs or the charged voltage is provided with the panel capacitor Cp.
The first address driving part 36A includes some fifth switches S5 and the sixth switches S6. The fifth switches S5 are connected to the electric power recovery device 40, and the sixth switches S6 are connected to the ground voltage GND. The fifth switches S5 are turned on when data pulses are provided, and they are turned off when data pulses are not provided. On the other hand, the electric power recovery device, which is formed on the anterior end of the second address driving part 36B, is formed symmetrically with the first address driving part 36A and the electric power recovery device 40 around the panel capacitor Cp.
FIG. 5 is timing diagram, which illustrates the on/off timing of each switch that are illustrated in FIG. 4 and a voltage value that is provided with the panel capacitor.
An action process of the electric power recovery device 40 is now explained in detail in reference to FIGS. 4 and 5.
Firstly, it is assumed that a voltage charged in the panel capacitor Cp before a T1 period has a voltage value of zero. It is also assumed that a voltage of Vd/2 is charged in the energy recovery capacitor Cs.
In the T1 period, the first switch S1 and the fifth switches S5 are turned on. At this time, if the discharge cell is not selected, in other words, if data pulses are not provided with the address electrode lines X, the fifth switches S5 sustain the off state. If the first switch S1 and the fifth switches S5 are turned on, a current path, which connects the energy recovery capacitor Cs and the panel capacitor Cp through the first switch S1, the inductor L, and the fifth switches S5, is formed. Accordingly, voltage charged in the energy recovery capacitor Cs is provided with the panel capacitor Cp. At this time, the voltage Vd powers the panel capacitor Cp with voltage, because the inductor L and the panel capacitor Cp form a series-resonant circuit.
In a T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, voltage of the address voltage Vd powers the panel capacitor Cp with voltage. The address voltage Vd, which is provided in the T2 period, prevents voltage of the panel capacitor from falling below the address voltage Vd, and accordingly a stable address discharge can be generated. On the other hand, driving power, which is externally provided to generate the address discharge, is minimized, because voltage of the panel capacitor Cp is raised up to the address voltage Vd in the T1 period.
In a T3 period, the first switch S1 is turned off, and the second switch S2 sustains the on state. Accordingly, the panel capacitor Cp sustains the address voltage Vd in the T3 period.
In a T4 period, the second switch S2 is turned off, and third switch S3 is turned on. If the third switch S3 is turned on, a current path, which connects the panel capacitor Cp and the energy recovery capacitor Cs through the fifth switch S5, the inductor L, and the third switch S3, is formed, and voltage charged in the panel capacitor Cp is recovered by the energy recovery capacitor Cs.
In a T5 period, when the third switch S3 and the fifth switches S5 are turned off, the fourth switch S4 and the sixth switches S6 are turned on. If the fourth switch S4 and the sixth switches S6 are turned on, a current path that connects the ground voltage GND and the panel capacitor Cp is formed, and voltage value of the panel capacitor Cp descends to zero. In fact, an existing electric power recovery device repeats the action process of the T1 through T5 period and simultaneously provides data pulses with the panel capacitor Cp.
However, a data pulse that is provided by the existing electric power recovery device has the wide pulse width. Therefore, the data pulse has a drawback that it cannot be used for the high-speed addressing. This is now explained in detail in reference to FIG. 6. Firstly, the data pulse that is provided by an existing electric power recovery device is divided into a T1 period that voltage is charged in the panel capacitor Cp, a T2 period that address voltage is provided with the panel capacitor Cp, a T3 period that voltage charged in the panel capacitor Cp is recovered and is charged in the energy recovery capacitor Cs, and a T4 period that voltage value in the panel capacitor Cp is descended to zero.
Here, what is actually required for the address discharge is the T2 period, and the T1 period, the T2 period, and the T3 period are the preparatory periods to charge voltage in the capacitors Cs and Cp. In other words, data pulse that is provided by an existing electric power recovery device cannot be used for the high-speed addressing, because it has the preparatory periods T1, T3, and T4 other than the T2 period that is actually required for the address discharge.
To resolve this problem, a electric power recovery device 50A is suggested as is illustrated in FIG. 7.
Referring to FIG. 7, the electric power recovery device 50A includes the inductor L that is connected between a first address driving part 36A and an energy recovery capacitor Cs, the first switch S1 and the third switch S3 that are connected between the energy recovery capacitor Cs and the inductor L in parallel, and the second switch S2 that is connected between the inductor L and the first address driving part 36A. The panel capacitor Cp expresses the electric capacitance of the discharge cell equivalently.
The second switch S2 is connected to the address voltage Vd. The energy recovery capacitor Cs recovers and charges voltage that is charged in the panel capacitor Cp, and simultaneously re-powers the panel capacitor Cp with the charged voltage. At this time, voltage charged in the energy recovery capacitor Cs varies according to provided data. The inductor L and the panel capacitor Cp form the resonance circuit. If the first though third switches S1 through S3 are turned on and turned off, voltage is charged in the energy recovery capacitor Cs or the charged voltage is provided with the panel capacitor Cp.
The first address driving part 36A includes some fourth switches S4 and fifth switches S5. The fourth switches S4 are connected to the electric power recovery device 50A, and the fifth switches S5 are connected to ground voltage GND. The fourth switches S4 are turned on when data pulse is provided, and they are turned off when data pulse is not provided. On the other hand, the electric power recovery device, which is formed on the anterior end of the second address driving part 36B, is formed symmetrically with the first address driving part 36A and the electric power recovery device 40 around the panel capacitor Cp.
FIG. 8 is a timing diagram, which illustrates the on/off timing of each of the switches illustrated in FIG. 7 and the voltage value provided with the panel capacitor.
An action process of the electric power recovery device 50A in the present invention is now explained in reference to FIGS. 7 and 8. Firstly, it is assumed that voltage charged in the panel capacitor Cp before the T1 period has voltage value of zero. It is also assumed that given voltage is charged in the energy recovery capacitor Cs.
In a T1 period, the first switch S1 and the fourth switches S4 are turned on. At this time, if the discharge cell is not selected, in other words, if data pulse is not provided with the panel capacitor Cp, the fourth switches S4 sustain the off state. If the first switch S1 and the fourth switches S4 are turned on, a current path, which connects the energy recovery capacitor Cs and the panel capacitor Cp through the first switch S1, the inductor L, and the fourth switches S4, is formed. The inductor L and the panel capacitor Cp form the series resonance circuit, and address voltage Vd is provided with the panel capacitor Cp.
In a T2 period, the second switch S2 is turned on. If the second switch S2 is turned on, the address voltage Vd is provided with the panel capacitor Cp. At this time, the address voltage Vd, which is provided with the panel capacitor Cp, prevents voltage in the panel capacitor Cp from falling below the address voltage Vd, and accordingly the address discharge can be normally generated.
In a T3 period, the first switch S1 is turned off and the second switch S2 sustains the on state. Therefore, the address voltage Vd is sustained in the panel capacitor Cp during the T3 period.
In a T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path, which connects the panel capacitor Cp and the energy recovery capacitor Cs though the fourth switches S4, the inductor L, and the third switch S3, is formed, and voltage charged in the panel capacitor Cp is recovered by the energy recovery capacitor Cs.
In a T5 period, address pulse is provided with the address electrode lines X by repeating the action in the T1 period. In fact, the data pulse provided with the panel capacitor Cp can be obtained, while the action processes in the T1 through T4 period are periodically repeated.
Also, to resolve the problem that relates to the existing electric power recovery device 40 illustrated in FIG. 4, an electric power recovery device 50B is suggested as is illustrated in FIG. 9.
Referring to FIG. 9, the electric power recovery device 50B includes a inductor L and a first switch S1 that are connected between a first address driving part 36A and a source capacitor Cs, and a second switch S2 that is connected between the inductor L and the first address driving part 36A. When the electric power recovery device 50B illustrated in FIG. 9 is compared with the electric power recovery device 40 illustrated in FIG. 4, it is clear that two switches are connected between the inductor L and the source capacitor Cs in parallel in the electric power recovery device 40, but the first switch S1 is serially connected between the inductor L and the source capacitor Cs in the electric power recovery device 50B. The first address driving part 36A is comprised of the third switch S3 and the fourth switch S4 that are connected between the electric power recovery device 50B and the panel capacitor Cp. The panel capacitor Cp equivalently expresses the electric capacitance formed between each of the address electrode lines X1 through Xn. The second switch S2 is connected to the address voltage Vd, and the fourth switch S4 is connected to the ground voltage GND. The source capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp in the address discharge, and re-power the panel capacitor Cp with the charged voltage. The source capacitor Cs has large capacitance so that voltage of Vd/2 that corresponds to half of the address voltage Vd can be charged. The inductor L and the panel capacitor Cp form a resonance circuit. The third switch S3 is turned on when data pulse is provided, and it is turned off when data pulse is not provided. The electric power recovery device, which is formed on the anterior end of the second address driving part 36B, is formed symmetrically with the first address driving part 36A around the panel capacitor Cp.
FIG. 10 is a timing chart illustrating the on/off timing of each of the switches illustrated in FIG. 9, and a waveform chart illustrating the output by the panel capacitor.
An action process of an electric power recovery device 50B is now explained in reference to FIGS. 9 and 10.
Firstly, it is assumed that voltage charged among address electrode lines X before the T1 period, in other words, voltage charged in the panel capacitor Cp, has voltage value of zero. It is also assumed that voltage of Vd/2 is charged in the source capacitor Cs.
In a T1 period, the first switch S1 and the third switch S3 are turned on. At this time, if the discharge cell is not selected, in other words, if data pulse is not provided with the address electrode lines X, the third switch S3 sustains the off state. If the first switch S1 and the third switch S3 are turned on, a current path that connects the source capacitor Cs and the panel capacitor Cp through the first switch S1, inductor L, and the third switch S3. At this time, the inductor L and the panel capacitor Cp form a series resonance circuit. In the series resonance circuit, voltage in the panel capacitor Cp rises to the address voltage Vd, which is twice as much as voltage in the source capacitor Cs, by the charge and the discharge of the current in the inductor L, because voltage of V/d2 is charged in the source capacitor Cs.
In a T2 period, the second switch S2 is turned on. If the second switch S2 is turned on, the address voltage is provided with the address electrode lines X. Address voltage, which is provided with the address electrode lines X, prevents voltage in the panel capacitor Cs from falling below the address voltage Vd, and accordingly the address discharge can be normally generated. At this time, driving power, which is externally provided to generate the address discharge, is minimized, because voltage in the panel capacitor rises to the address voltage Vd in the T1 period.
In a T3 period, the first switch S1 is turned off, and the address voltage Vd that is provided with the address electrode lines X is sustained.
In a T4 period, the second switch S2 is turned off, and the first switch S1 is turned on. If the first switch S1 is turned on, a current path, which connects the panel capacitor Cp and the source capacitor Cs through the third switch S3, the inductor L, and the first switch S1, is formed, and voltage that is charged in the panel capacitor Cp is recovered by the source capacitor Cs. Voltage in the panel capacitor descends while the panel capacitor Cp is discharged, and at the same time, voltage of Vd/2 is charged in the source capacitor Cs. At this time, a current patch, which connects the source capacitor Cs and the panel capacitor Cp through the first switch S1, the inductor L, and the third switch S3, is formed, because the first switch S1 sustains the on state. That is, the source capacitor starts discharging the panel capacitor Cp after voltage of Vd/2 is charged as is the case with the T5 period. The fourth switch S4 is turned on, if data pulse is not provided with the address electrode lines X. In fact, the data pulse that is provided with the address electrode lines X can be obtained, while the action processes in the T1 through T4 period are periodically repeated.
As is the case with FIG. 11, the data pulse, which is generated in the electric power recovery device 50A illustrated in FIG. 7 and the electric power recovery device 50B illustrated in FIG. 9, is divided into a T1 period that voltage is charged in the panel capacitor Cp, a T2 period that the address voltage Vd is provided with the panel capacitor Cp, and a T3 period that the voltage charged in the panel capacitor Cp is recovered and is charged in the energy recovery capacitor Cs. That is, it is possible to execute the high-speed addressing in the electric power recovery device 50A illustrated in FIG. 7 and the electric power recovery device 50B illustrated in FIG. 9, because the T4 period that voltage in the energy recovery capacitor Cs is sustained at the level of Vd/2 is removed in the electric power recovery devices 50A and 50B.
However, these electric power recovery devices 50A and 50B are operated whenever data pulse is provided with each of the address electrode lines. Therefore, if the small number of data pulse is provided with each of the address electrode lines, in other words, if there is small number of data-loading in each of the address electrode lines, this causes a problem that the power consumption requires more power when the electric power recovery devices 50A and 50B are driven. That is, if the small amount of data-loading is executed in the process to recover power by the electric power recovery devices 50A and 50B to lower power consumption, this causes a problem that power to drive each of parts in the electric power recovery devices 50A and 50B comes to be larger than power to provide data pulse, and accordingly power consumption is increased.